A phase-locked loop (PLL) is an electrical circuit that controls an oscillator so that the oscillator maintains a constant phase angle relative to a reference signal. In general, a PLL is formed by a phase detector, a charge pump, a low pass filter, and a voltage-controlled oscillator (VCO). The PLL receives an input signal and operates to control the VCO to lock to the frequency indicated by the input signal so that the output oscillating signal of the VCO maintains a fixed phase relationship with the input signal.
FIG. 1 is a schematic diagram of a conventional phase-locked loop (PLL) circuit. Referring to FIG. 1, a phase-locked loop (PLL) circuit 10 receives an input signal 12 having an input frequency fin and generates an output signal 22 having an output frequency fout where the output signal 22 has a fixed relation to the phase of the input signal 12. The PLL circuit 10 includes a phase and frequency detector (PFD) 14, a charge pump 16, a low pass filter 18 and a voltage controlled oscillator (VCO) 20. The low pass filter 18, also referred to as a loop filter, is typically implemented as a serial connection of a capacitor C1 and a resistor R1. PLL circuit 10 also includes a feedback frequency divider 24 forming a negative feedback loop. The feedback frequency divider 24 receives the output signal 22 and generates a feedback signal 26 having a divided-down feedback frequency ffb. The feedback signal 26 is coupled to the phase and frequency detector 14 to form the feedback loop.
The operation of PLL 10 is well known. The phase and frequency detector 14 compares the phase difference between the input signal 12 and the feedback signal 26. The phase difference is used to control the charge pump 16 which drives a control voltage node 17 to generate a control voltage VCTL for controlling the VCO 20. The control voltage node 17 is coupled to the low-pass filter 18 to filter out high frequency changes at the control voltage VCTL. The voltage-controlled oscillator (VCO) 20 generates the output signal 22 having a fixed relation to the phase of the input signal. The output signal 22 is fed back to the phase and frequency detector 14 through the feedback frequency divider 24.
For stability of operation and good transient response, it is generally desirable for the PLL circuit to have a constant damping ratio. The damping ratio of a PLL circuit using charge pump is generally a function of the resistance (R1) in the low pass filter, the current ICP provided by the charge pump and the gain of the VCO. However, because of fabrication process variations and operational voltage and temperature variations, the resistance in the low pass filter and the charge pump current can have large variations, such as 30% or more. As a result, the damping ratio in a conventional PLL circuit is not constant but instead can vary over a wide range due to the manufacturing process or can vary during circuit operation. The damping ratio variation of the conventional PLL circuit negatively impacts the stability and transient response of the circuit.